Cross-Sectioning Techniques in Semiconductor & Microelectronics Failure Analysis
Watson Analytical Engineering Team · May 2026 · ~18 min read · Intermediate Level
Topics: Semiconductor Failure Analysis, Physical Failure Analysis, FIB Milling, BIB Ion Milling, Mechanical Polishing, Chemical Etching, Cross-Sectioning, TEM Preparation
Cross-sectioning is the definitive step that transitions a semiconductor or microelectronics failure analysis investigation from electrical fault isolation to physical root-cause identification. Selecting the right technique — and sequencing it correctly — is one of the most consequential decisions an FA engineer makes.
A poorly chosen cross-section destroys the defect site, introduces preparation artifacts, or fails to deliver the resolution required for the downstream analytical technique. By contrast, a well-designed preparation strategy yields a clean, interpretable result on the first attempt — accelerating root-cause identification and corrective action.
This article covers the four cross-sectioning methods that address the vast majority of FA scenarios in a modern semiconductor or microelectronics failure analysis laboratory: mechanical polishing and lapping, focused ion beam (FIB) milling, broad ion beam (BIB) ion milling, and chemical and wet etching.
ℹ️ Who This Article Is For
Written for mid-level FA engineers with working familiarity with SEM/optical inspection, electrical fault isolation techniques (OBIRCH, EMMI, LVI), and basic semiconductor package and interconnect architectures. New to FA? Start with Watson's Introduction to Failure Analysis primer.
In This Article
- Why Technique Selection Matters
- Mechanical Polishing & Lapping
- Focused Ion Beam (FIB) Milling
- Broad Ion Beam (BIB) Milling
- Chemical & Wet Etching
- Comparing the Techniques
- Selection & Workflows
- References
Why Cross-Section Technique Selection Matters
The target of a cross-section varies enormously: a single tungsten contact plug at a 5 nm node, a fatigue crack propagating through a copper pillar, a delamination buried beneath 500 µm of epoxy mold compound, or a voided solder joint in a BGA package. Each scenario places fundamentally different demands on spatial precision, area coverage, material compatibility, and turnaround time.
The four techniques covered here are complementary, not competitive. Expert physical failure analysis practice integrates them into sequenced, multi-technique workflows calibrated to each case. Understanding the operating envelope of each is the prerequisite for designing those workflows effectively.
Mechanical Polishing and Lapping in Semiconductor Failure Analysis
| Technique Snapshot — Mechanical Polishing / Lapping | |
|---|---|
| Spatial Resolution | ~1–5 µm (optical); ~0.5 µm (SEM post-polish) |
| Area Coverage | Millimeters to centimeters |
| Site Specificity | Low — fiducial or X-ray depth control |
| Typical Turnaround | 30 minutes to 3 hours |
Operating Principle
The sample — typically cold- or hot-mounted in epoxy resin — is ground through a decreasing abrasive sequence: silicon carbide papers (400–4000 grit), diamond lapping films (9 µm → 1 µm → 0.1 µm), and colloidal silica or alumina for final polish. Automated polishing stations (Struers TegraPol, Buehler AutoMet) provide controlled load, speed, and head rotation for improved planarity and repeatability vs. hand polishing.
Depth control — stopping accurately at the target feature — is the central challenge. Common approaches: sectioning to a known fiducial, periodic SEM or optical inspection intervals, and X-ray imaging of remaining wall thickness before committing to final polishing passes.
Where Mechanical Polishing Excels in Semiconductor FA
- Package-level failures — solder joint fatigue, wire bond liftoff, die attach delamination, mold compound cracking
- Large-area surveys before committing to a time-intensive FIB session
- Defect feature size ≥ 1 µm — mechanical polishing is the fastest, most cost-effective approach
- High-throughput screening — reliability lot qualification, incoming quality control
Preparation Artifacts — What to Watch For
- Smearing: Ductile metals (Al, Cu) deform across the cut face. Mitigation: low-ductility abrasive sequence; colloidal silica final polish; BIB ion polish for cleanup.
- Pullout: Hard particles (W, carbides) dislodge, leaving voids that mimic real defects. Mitigation: low-load final-stage polishing; adequate resin impregnation before mounting.
- Edge rounding: Die–resin interface differential polishing. Mitigation: harder mounting resins; dummy edge pieces.
- False depth: Resin on the face mimics reaching target depth under optical inspection. Mitigation: verify in SEM at low voltage.
⚠️ Sub-Micron Limitation
Mechanical polishing is not a substitute for FIB or BIB at feature sizes below approximately 1 µm. Attempting to use mechanical methods at advanced-node device sites will almost certainly introduce artifacts that obscure or destroy the defect.
Focused Ion Beam (FIB) Milling for Semiconductor Failure Analysis
| Technique Snapshot — Focused Ion Beam (FIB) — Dual-Beam SEM/FIB | |
|---|---|
| Spatial Resolution | < 5 nm imaging; < 10 nm milling spot |
| Area Coverage | < 50 µm × 50 µm per section |
| Site Specificity | Very High — coordinate-targeted from SEM or fault isolation map |
| Typical Turnaround | 1–4 hrs (section); 4–8 hrs (TEM lamella) |
Operating Principle
Modern FA labs use dual-beam instruments combining a focused ion beam column (Ga⁺, or Xe⁺ in plasma FIB systems) with a high-resolution field-emission SEM at a fixed 52° angle. This geometry enables the FIB to mill while the SEM images the cross-section face in real time — simultaneous depth control and defect visualization.
Standard workflow: (1) platinum or carbon protective cap via gas injection system (GIS); (2) bulk trenches at high current (several nA); (3) sequential low-current cleaning passes (200 pA → 50 pA → 10 pA) for sub-10 nm surface roughness; (4) SEM/EDS/EBSD analysis; (5) optional TEM lamella lift-out.
FIB Lift-Out for TEM Lamella Preparation
For cases requiring TEM-level resolution — advanced-node gate stacks, metal grain boundary characterization, interfacial phase analysis — FIB lift-out is the industry-standard preparation method. A thin lamella (~100 nm, ~15 µm wide) is milled, cut free, transferred to a TEM grid via in-situ micromanipulator, and thinned to electron transparency in final FIB passes.
Key parameters to manage: gallium implantation zone (~20–30 nm amorphous damage layer; reduced by low-kV final cleaning); curtaining artifacts from differential milling rates; lamella thickness uniformity (target 80–120 nm for STEM; 50–80 nm for conventional TEM).
Xenon Plasma FIB (PFIB) — When to Consider It
Xe⁺ plasma FIB systems offer beam currents up to ~2 µA — approximately 50× higher than conventional Ga FIB — enabling cross-sections covering 200 µm × 200 µm or more. PFIB is increasingly preferred for advanced packaging cross-sections, large-die surveys, and GaAs-based devices where Ga background contamination would compromise EDS compositional data.
⚠️ FIB Is Not a Survey Technique
If fault isolation coordinates have more than ~5 µm uncertainty, survey with mechanical or BIB first. Gallium EDS signal is always present as a preparation artifact — it is not a real material constituent of your sample.
→ Article 3: FIB Milling and Dual-Beam SEM/FIB — Procedures, TEM Lift-Out, and Artifact Management
Broad Ion Beam (BIB) Milling / Ion Milling in Semiconductor FA
| Technique Snapshot — BIB / Argon Ion Milling (Cross-Section Ion Polishing) | |
|---|---|
| Surface Roughness | ~5–50 nm; sub-nm grain structure revealed |
| Area Coverage | Up to ~5 mm × 3 mm per session |
| Site Specificity | Moderate — requires mechanical pre-section to within ~100 µm |
| Typical Turnaround | 2–12 hours including mechanical pre-section |
Operating Principle
BIB instruments (JEOL IB-09010CP, Hitachi IM-4000Plus) direct a broad, defocused argon ion beam at a mechanically pre-sectioned sample face at low angle of incidence (0–10° from the surface). The beam uniformly sputters the exposed face, removing the mechanical damage layer — polishing compounds, resin smear, subsurface strain, cold-worked metal — to reveal a pristine, low-damage crystallographic surface across a millimeter-scale area.
Where BIB Outperforms Mechanical Polishing for Semiconductor FA
- EBSD grain orientation mapping: Requires strain-free, flat surface with <5 nm roughness — unachievable by mechanical polishing alone. BIB delivers this reliably.
- Heterogeneous material systems: MLCCs (BaTiO₃/Ni electrode), PCB fiber-resin composites, ceramic-metal interfaces — materials with large hardness differences polish at different rates mechanically, creating relief and phase rounding. BIB polishes all phases flat simultaneously.
- Thin film stack preservation: BIB maintains layer thicknesses and interfaces with much lower distortion than mechanical methods.
- Hard materials: SiC, AlN, alumina — BIB achieves scratch-free surfaces without subsurface crack propagation from mechanical load.
Chemical and Wet Etching for Semiconductor Cross-Section FA
| Technique Snapshot — Chemical / Wet Etching (Selective Dissolution) | |
|---|---|
| Role in Workflow | Supplementary — applied after mechanical or BIB cross-section |
| Area Coverage | Millimeters to centimeters; batch-compatible |
| Primary Output | Enhanced phase and layer contrast for optical and SEM analysis |
| Site Specificity | Low — applied globally across the prepared face |
Role in Physical Failure Analysis
Chemical etching is almost never used as a standalone cross-sectioning method. Instead, it serves as a powerful contrast-enhancement step applied to an already-prepared cross-section face. Selective etchants dissolve specific material phases preferentially, revealing grain boundaries, p-n junction positions, epitaxial layer boundaries, dislocations, and stacking faults that are invisible under unetched SEM or optical inspection.
Common Etchant Systems for Semiconductor Physical Failure Analysis
| Etchant | Target Material | FA Application |
|---|---|---|
| Secco Etch (HF + K₂Cr₂O₇) | Silicon | Dislocations, stacking faults, EPI/substrate boundary |
| Wright Etch | Silicon (p and n-type) | Grain boundaries, crystal defect delineation |
| Dilute HF (1–10%) | SiO₂, native oxide | Selective oxide removal; interface exposure |
| Buffered Oxide Etch (BOE) | SiO₂ (controlled rate) | Controlled oxide removal; contact hole inspection |
| HNO₃ + HF (Murakami's) | III-V (GaAs, InP) | Phase delineation in compound semiconductor devices |
| FeCl₃ / HCl | Copper | Cu grain structure and recrystallization mapping |
| Kroll's Reagent | Titanium, TiN | Barrier layer delineation in interconnects |
| Fuming HNO₃ | Organic encapsulants | Decapsulation; mold compound removal from die surface |
⚠️ Chemical Safety — Mandatory Training Required
Hydrofluoric acid in any concentration requires site-specific HF safety certification, HF-rated PPE, and access to calcium gluconate antidote gel before use. Fuming nitric acid requires a ventilated enclosure and chemical splash protection. No wet etching may be performed without laboratory chemical safety certification for each reagent.
→ Article 5: Chemical and Wet Etching — Etchant Selection, Rate Control, and Safety Protocols
Comparing the Four Cross-Sectioning Techniques
The table below compares all four techniques across the criteria most relevant to FA technique selection. Values represent typical laboratory conditions — actual performance is instrument-, operator-, and material-dependent.
| Technique | Prep Time | Spatial Res. | Area | Site Specificity | Damage | TEM-Ready? |
|---|---|---|---|---|---|---|
| Mechanical Polishing | Min–Hrs | ~1–5 µm | mm–cm | Low | Low–Moderate | No |
| FIB Milling | Min–Hrs | < 5 nm | < 50 µm² | Very High | Low (local) | Yes (lift-out) |
| BIB / Ion Milling | Hours | ~5–50 nm | mm–cm | Moderate | Very Low | No |
| Chemical Etching | Min–Hrs | ~0.1–5 µm | mm–cm | Low | Moderate | No |
Technique Selection and Multi-Technique Workflows
Scenario-Based Decision Framework
| Analytical Objective | Primary Technique | Rationale |
|---|---|---|
| Nanometer-precision site-specific section or TEM lamella | FIB (dual-beam) | Only technique combining precise navigation, nm-milling, and in-situ SEM monitoring |
| Large-area flat section for EBSD / EDS mapping | BIB / Ion Milling | mm-scale, damage-free faces across heterogeneous materials |
| Rapid bulk deprocessing to approach depth of interest | Mechanical Polishing | Fastest removal; low cost; refined by subsequent BIB or FIB step |
| Layer boundary delineation after mechanical section | Chemical Etching | Selective dissolution highlights interfaces invisible under SEM contrast alone |
| Void, delamination, or crack in package interconnects | Mechanical + BIB or FIB | Mechanical for approach; BIB for survey surface; FIB if nm-precision needed |
| High-k / metal gate or FinFET stack characterization | FIB lift-out → TEM | Gate stack dimensions at advanced nodes require atomic-resolution TEM |
| Multi-layer ceramic or composite substrate analysis | BIB / Ion Milling | Heterogeneous materials require ion polishing for a flat, artifact-free face |
The Standard Multi-Technique FA Workflow
Most advanced-node device and interconnect FA cases follow a sequential multi-technique workflow. Understanding the handoff points is the key skill:
- Fault Isolation & Site Identification — Electrical FA (OBIRCH, EMMI, LVI, OBIC) narrows the region of interest to a specific die location or package zone.
- Technique Selection — Select primary and complementary techniques based on resolution, area, material, and downstream analytical method.
- Coarse Removal (if required) — Mechanical polishing brings the sample within ~50–200 µm of the target depth.
- Fine / Precision Preparation — FIB for site-specific nm-scale sections or TEM lamellae; BIB for large-area, low-damage surface polish.
- Analytical Imaging & Characterization — SEM, EDS, EBSD, TEM/STEM, or optical microscopy on the prepared cross-section face.
- Documentation & Root-Cause Correlation — Cross-section images correlated with electrical data and process history to establish root cause and corrective action.
Need expert cross-sectioning and physical failure analysis support for your semiconductor or microelectronics components?
Watson FA Lab Cross-Sectioning Series
- Overview of Cross-Sectioning Techniques (this article)
- Mechanical Polishing and Lapping — Procedures & Best Practices
- FIB Milling and Dual-Beam SEM/FIB — Procedures & TEM Lift-Out
- BIB Ion Milling — Procedures, EBSD Surface Preparation & Applications
- Chemical & Wet Etching — Etchant Selection, Rate Control & Safety
References
- Shea, P. (Ed.). Microelectronics Failure Analysis Desk Reference, 7th ed. ASM International, 2019.
- Giannuzzi, L.A. & Stevie, F.A. (Eds.). Introduction to Focused Ion Beams. Springer, 2005.
- Goldstein, J.I. et al. Scanning Electron Microscopy and X-Ray Microanalysis, 4th ed. Springer, 2018.
- Vander Voort, G.F. Metallographic Principles and Practice. ASM International, 1999.
- Phaneuf, M.W. "Applications of focused ion beam microscopy to materials science specimens." Micron, 30(3), 1999, pp. 277–288.
- EDFAS (Electronic Device Failure Analysis Society) — edfas.org
Related Topics: semiconductor failure analysis, physical failure analysis, microelectronics failure analysis, cross-sectioning techniques, FIB milling semiconductor, focused ion beam FA, broad ion beam milling, BIB ion polishing, mechanical polishing FA, chemical wet etching, TEM lamella preparation, SEM cross section, EBSD sample preparation, package failure analysis, interconnect failure analysis, FinFET failure analysis, flip chip FA, advanced packaging FA
