Integrated circuit delayering removes metal and dielectric layers one at a time to expose the structures and defects beneath them. Each layer is imaged and documented before the next is removed, revealing physical defects found during fault isolation and documenting device construction for construction analysis, counterfeit verification, and intellectual property investigations.
Delayering is also referred to as deprocessing, die deprocessing, layer-by-layer delayering, and parallel lapping.
Applications
- Exposing physical defects at sites localized by fault isolation
- Construction analysis and process verification
- Counterfeit die verification against authentic references
- Intellectual property and patent infringement investigations
- Gate oxide, contact, and via inspection
Delayering Methods
Each device is delayered with the method or combination of methods best suited to its materials and the goal of the analysis:
- Plasma (RIE): reactive ion etching selectively removes dielectric layers such as oxides, nitrides, and polyimide passivation with precise control.
- Wet chemical: selective etchants remove specific metals or dielectrics while leaving underlying layers intact.
- Mechanical: parallel lapping and polishing remove layers uniformly across the die, which is effective for planarized multi-layer devices.
Combining methods lets each layer be removed with the technique that gives the cleanest result, preserving the features needed for analysis.
Layer-by-Layer Documentation
After each layer is removed, the exposed surface is imaged with optical microscopy and scanning electron microscopy. The resulting image set documents every metal and dielectric layer, so defects can be traced to the layer where they originate and device construction can be compared against reference parts or design data.
Turnaround and Deliverables
Typical turnaround for delayering is 2 to 3 days, depending on the number of layers and the analysis required. Results are documented with layer-by-layer images in an engineering report.
Related Services
- Scanning Electron Microscopy (SEM/EDX)
- Package Decapsulation
- Focused Ion Beam (FIB) Analysis
- High Power Reflected Optical Microscopy
Frequently Asked Questions
What is IC delayering?
IC delayering removes the metal and dielectric layers of an integrated circuit one at a time, imaging each layer to expose defects and document how the device was built.
Which delayering method is best?
It depends on the device materials and the goal of the analysis. Plasma etching is selective for dielectrics, wet chemistry is selective for specific metals, and mechanical lapping removes layers uniformly. Most analyses use a combination.
Can delayering support patent or IP litigation?
Yes. Layer-by-layer documentation of device construction provides physical evidence for intellectual property and patent investigations.
Request Delayering
Watson Analytical is an ISO 9001:2015 certified, ITAR-registered failure analysis laboratory in San Diego, California, serving semiconductor, defense, space, biomedical, and litigation customers. Contact us to discuss your device and request a quote.