Semiconductor Fault Isolation

Semiconductor fault isolation localizes the exact site of an electrical failure on an integrated circuit, so that physical analysis can be directed to the right location. Watson Analytical operates a multi-sensor fault isolation system that combines photon emission, laser stimulation, thermal imaging, and dynamic techniques in a single platform, allowing analysts to move between techniques on the same device without remounting it.

Fault isolation is also referred to as electrical fault isolation (EFI), fault localization, and defect localization.

Fault Isolation Techniques

Emission and Thermal

• Photon Emission Microscopy (PEM/EMMI): junction leakage, oxide breakdown, latch-up, and saturated transistors.
• Modulated Thermography: shorts, latch-up, and abnormal power dissipation.

Static Laser Stimulation

• XIVA™ and Lock-in XIVA™: metal shorts, resistive opens, and leakage paths (related to OBIRCH and TIVA).
• OBIC and Lock-in OBIC: damaged junctions, gate oxide shorts, and junction leakage.

Dynamic Laser Stimulation

• Soft Defect Localization (SDL): resistive defects behind marginal functional failures (also known as thermal DALS).
• Laser Assisted Device Alteration (LADA): speed paths and timing-critical transistors (also known as photoelectric DALS).

Sample Preparation for Backside Analysis

• Area Defined Backside Preparation: direct optical access through the substrate on dense and flip-chip devices.
• Area Defined Die Thinning: improved infrared transmission for LADA and other backside techniques.

Choosing the Right Technique

The failure signature determines where to start:

• Elevated leakage or a short: start with PEM and thermography, then XIVA™ if the defect does not emit.
• Very low-level leakage: lock-in XIVA™ or lock-in OBIC.
• Junction or ESD damage: PEM and OBIC.
• Functional, timing, or marginal failure: SDL for resistive defects and LADA for timing-critical transistors.

Once the failure site is localized, physical analysis such as FIB cross-sectioning, delayering, and SEM/EDX reveals the physical defect and its root cause.

Turnaround and Deliverables

Typical turnaround for fault isolation is 3 to 5 days, depending on device complexity, test setup, and the sample preparation required. Results are documented with annotated fault localization images in an engineering report.

Frequently Asked Questions

What is fault isolation in failure analysis?

Fault isolation is the step that localizes an electrical failure to a specific site on the die, using emission, laser, thermal, or dynamic techniques, before physical analysis exposes the defect.

Which fault isolation technique do I need?

It depends on the failure signature. Send us the failure description and electrical data, and our engineers will recommend the technique or sequence of techniques most likely to localize the defect.

Can fault isolation be performed through the backside of the die?

Yes. After backside preparation, PEM, XIVA™, OBIC, SDL, and LADA can all be performed through the substrate, which is required for flip-chip devices and dense multi-layer designs.

Request Fault Isolation

Watson Analytical is an ISO 9001:2015 certified, ITAR-registered failure analysis laboratory in San Diego, California, serving semiconductor, defense, space, biomedical, and litigation customers. Contact us to discuss your failure and request a quote.